1. Field of the Invention
The present invention relates to control circuits and more specifically relates to a control circuit with short circuit protection for current sense terminal of power converter.
2. Description of Related Art
Various power converters have been widely used to provide regulated voltage and current. For the sake of safety, an over-power protection has to provide for protecting both power converter itself and the system. The output power is thus required to be limited for controlling the power converter. Normally, limiting the switching current of the power converter would control the output power. FIG. 1 shows a traditional power converter. The power converter includes a control circuit 10, which coupled to the output voltage VO of the power converter to generate a switching signal SW at a switching terminal SW of the control circuit 10 for regulating the output voltage VO. The switching signal SW is transmitted to a power switch 11 to switch a transformer 12 and control the energy transferred through the transformer 12. As the switching signal SW becomes enable, a switching current IP of the power switch 11 is generated accordingly. The switching current IP is expressed as,
                              I          P                =                                            V              IN                                      L              P                                ×                      T            ON                                              (        1        )            
where VIN is an input voltage applied to the transformer 10; LP is the primary inductance of the transformer 12; and TON is an on-time of the switching signal SW.
The switching current IP generates an input signal VI by a resistor 13. The input signal VI is transmitted to a current sense terminal VI of the control circuit 10. The output voltage VO is generated from the transformer 12 through a rectifier 14 and a capacitor 15. A reference voltage device 17 and a resistor 16 are connected in serial. The resistor 16 is connected to the output voltage VO. The reference voltage device 17 is connected to an optical isolator 18. The optical isolator 18 generates a feedback signal VFB which is coupled to the control circuit 10.
FIG. 2 shows a conventional control circuit 10 of the power converter. A comparator 101 is coupled to receive the input signal VI representing the switching current IP of the power switch 11 (as shown in FIG. 1). Another input terminal of the comparator 101 is coupled to receive the feedback signal VFB to compare with the input signal VI for the current mode control. A resistor 108 is connected to bias the feedback signal VFB. The switching signal SW is turned off when the level of the input signal VI is higher than the level of the feedback signal VFB. A comparator 102 is coupled to receive the input signal VI as well and is utilized to limit the maximum current of the power switch 11. The comparator 102 compares the input signal VI with a current-limit threshold VTH. The power switch 11 is turned off cycle-by-cycle in response to the output of the comparator 102 when the current limit set by the current-limit threshold VTH is exceeded. The comparator 102 would limit the maximum value of the output power. The control circuit 10 generates the switching signal SW to drive power switch 11 in response to the feedback signal VFB for regulating the output voltage VO of the power converter. An oscillation circuit 103 (OSC) generates a clock signal PLS to the clock-input terminal CK of a flip-flop 104 through an inverter 105. The supply voltage VCC transmits to the D-input terminal D of the flip-flop 104. The reset-input R of the flip-flop 104 is connected to the output terminal of an AND gate 106. The input terminal of the AND gate 106 is connected to the output terminal the comparator 101. Another input terminal of the AND gate 106 is connected to the output terminal of the comparator 102. The output terminal Q of the flip-flop 104 is connected to a AND gate 107. Another input terminal of the AND gate 107 receives the clock signal PLS through the inverter 105. The AND gate 107 generates the switching signal SW from its output terminal. The switching signal SW is therefore enabled by the clock signal PLS periodically and is controlled by the feedback signal VFB. Besides, in order to protect the power switch 11, the switching signal SW is disabled when the switching current IP is higher than the current-limit threshold VTH.
However, a potential problem exists when the current sense terminal VI of the control circuit 10 is short-circuited as shown in FIG. 3. Both the feedback and the protection functions are disabled under this circumstance, which may cause the permanent damage to the power converter.